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HSDL-3210
IrDA(R) Compliant Low Power 1.15 Mbit/s Infrared Transceiver
Data Sheet
Description
The HSDL-3210 is one of a new generation of low-cost Infrared (IR) transceiver modules from Avago Technologies. It features one of the smallest footprint in the industry at 2.5 H x 8.0 W x 3.0 D mm. Although the supply voltage can range from 2.7 V to 3.6 V, the LED is driven by an internal constant current source of 60 mA at SIR data rates and 150 mA at MIR data rates. The HSDL-3210 incorporates the capability for adjustable optical power. The optical power can be adjusted lower when the nominal desired link distance is very short. At 5 cm link distance, only 6% of the full power is required. The HSDL-3210 supports the Serial Interface for Transceiver Control Specification that provides a common interface between the transceiver and controller. It is also designed to interface to input/ output logic circuits as low as 1.5 V.
Features
* Fully Compliant to IrDA 1.4 low power specification from 9.6 kbit/s to 1.15 Mbit/s * Ultra small surface mount package * Minimal height: 2.5 mm * VCC from 2.7 to 3.6 volts * Interface to 1.5 volts input/output logic circuits * Withstands 100 mVp-p power supply ripple typically * Adjustable optical power for link distance from 5 to 20 cm * Low shutdown current - 10 nA typical * Complete shutdown - TxD, RxD, PIN diode * Three optional external components * Temperature performance guaranteed, -25C to 85C * Integrated EMI shield * IEC60825-1 class 1 eye safe * Edge detection input - Prevents the LED from long turn on time
Applications
* Mobile telecom - Cellular phones - Pagers - Smart phones * Data communication - PDAs - Portable printers * Digital imaging - Digital cameras - Photo-imaging printers
Application Support Information
The Application Engineering group in Avago Technologies is available to assist you with the Technical understanding associated with HSDL-3210 infrared transceiver module. You can contact them through your local Avago sales representatives for additional details.
Ordering Information
Part Number HSDL-3210-021 Packaging Type Tape and Reel Package Front View Quantity 2500
Application Circuit
VLED 8
8 7 6 5 4 3 2 1
C1 6.8 F
TXD/SWDAT 7
ADJUSTABLE OPTICAL POWER
REAR VIEW
RXD/SRDAT 6
SHIELD
Figure 2. Rear view diagram with pin-out.
SD 5
SCLK 4
SERIAL TRANSCEIVER CONTROL
VCC 3
C2 1.0 F C3 0.47 F
I/O VCC 2
GND 1
Figure 1. Functional block diagram of HSDL-3210.
I/O Pin Configuration Table
Pin 1 2 3 4 5 6 7 Symbol GND IOVCC VCC SCLK SD RXD/SRDAT Description Ground Input/Output VCC Supply Voltage Serial Clock Shut Down Active High Receiver Data Output. Active Low Notes Connect to system ground. Connect to ASIC logic controller VCC voltage. Regulated, 2.7 to 3.6 Volts Use as clock input pin for programming mode. See Table 1 for details. This pin must be driven either high or low, do NOT float the pin. Output is a low pulse when a light pulse is received. SRDAT is the read data for the Serial Transceiver Control (STC). Do NOT float this pin. Logic High turns on the LED. If held high longer than ~20 s, the LED is turned off. SWDAT is the write data for the Serial Transceiver Control (STC). Do NOT float this pin. May be unregulated, 2.7 to 5.5 volts. Connect to system ground via a low inductance trace. For best performance, do not connect to GND directly at the part.
TXD/SWDAT Transmitter Data Input/ Serial Write Data VLED SHIELD LED Supply Voltage EMI Shield
8 -
2
Recommended Application Circuit Components
Component C1 C2 C3 Recommended Value 6.8 F, 20%, Tantalum 1.0 F, 20%, Tantalum 0.47 F, 20%, Ceramic Notes 1
Note: 1. C1, which is optional, must be placed within 0.7 cm of the HSDL-3210 to obtain optimum noise immunity.
Serial Interface for Transceiver Control
The Serial Interface for Transceiver Control (STC) is used to control and program the features of the transceiver. These features include input/output (I/O) control, optical power adjustment and shut down.
The STC requires three signals: a serial clock (SCLK) that is used for timing, and two unidirectional lines multiplexed with the transmitter (write) TXD/SWDAT and receiver (read) RXD/SRDAT infrared signal lines. The HSDL-3210 supports the write function to disable/enable
the TXD line, disable/enable the RXD line and 4-level optical power adjustment. A set of commands is provided to handle the programming control features. The general command format is shown in Figure 3. The HSDL-3210 STC Write Data Commands are shown in Table 1.
ADDRESS [2-0]
INDEX [3-0]
C
DATA
Figure 3. General command format.
Table 1. Serial Interface for Transceiver Control - Write Data Format
Address [2-0] IrDA Data -data rates SIR (2.4 to 115.2 Kbps) MIR (0.576, 1.152 Mbps) I/O Control SD Normal Mode SD Sleep Mode RXD disable RXD enable TXD disable TXD enable Optical Power Adjustment 10% link distance 25% link distance 50% link distance 100% link distance 3 000 000 000 000 0010 0010 0010 0010 1 1 1 1 00XXXXXX 01XXXXXX 10XXXXXX 11XXXXXX 000 000 000 000 000 000 0000 0000 0000 0000 0000 0000 1 1 1 1 1 1 XXXXXXX1 XXXXXXX0 XXXXXX0X XXXXXX1X XXXXX0XX XXXXX1XX 000 000 0001 0001 1 1 00000000 00000001 Index [3-0] C Data
Table 2. Serial Interface for Transceiver Control - Read Data Format
Address [2-0] IrDA Data -data rates SIR (2.4 to 115.2 Kbps) MIR (0.576, 1.152 Mbps) I/O Control SD Normal Mode SD Sleep Mode RXD disable RXD enable TXD disable TXD enable Optical Power Adjustment 10% link distance 25% link distance 50% link distance 100% link distance ID Manufacturer Product
.
Index [3-0] 0001 0001 0000 0000 0000 0000 0000 0000 0010 0010 0010 0010 1111 1111
C 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data 00000000 00000001 XXXXXXX0 XXXXXXX1 XXXXXX0X XXXXXX1X XXXXX0XX XXXXX1XX 00XXXXXX 01XXXXXX 10XXXXXX 11XXXXXX 00000001 01000001
000 000 000 000 000 000 000 000 000 000 000 000 000 000
Transceiver I/O Truth Table
STC SD Mode Normal Mode SCLK Low SD Low TXD High Low Sleep Mode Don't care Don't care High Don't care Don't care LED On Off Off Off Receiver Don't care IrDA Signal No Signal Don't care Don't care RXD Not Valid Low High High High 6 6 Notes 2,3 4,5
Notes: 2. If TXD is stuck in the high state, the LED will turn off after about 14 s. 3. RXD will echo the TXD signal while TXD is transmitting data. 4. In-Band IrDA signals and data rates 1.152 Mbps. 5. RXD Logic Low is pulsed response. 6. RXD Logic High during shutdown is a weak pull up (equivalent to an approximately 300 k resistor).
4
Caution: The BiCMOS inherent to this design of this component increases the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature LED Supply Voltage Supply Voltage Input/Output Voltage Input Voltage: TXD, SCLK, SD Output Voltage: RXD
For implementations where case to ambient thermal resistance is 50C/W. Symbol TS TA VLED VCC IOVCC VI VO Min. -40 -25 0 0 0 0 -0.5 Max. 100 85 6.5 6.5 VCC VCC+ 0.5 VCC+ 0.5 Units C C V V V V V
Recommended Operating Conditions
Parameter Operating Temperature Supply Voltage Logic Input Voltage for TXD ,SCLK, SD Logic High Receiver Input Irradiance EIH Logic High Logic Low Symbol Min. TA VCC VIH VIL EIH -25 2.7 2/3 IOVCC 0 0.0081 0.0225 Logic Low Receiver Input Input/Output Voltage Receiver Data Rate EIL IOVCC 1.5 0.0024 Max. 85 3.6 IOVCC 1/3 IOVCC 500 500 0.3 VCC 1.152 Units C V V V mW/cm2 mW/cm2 W/cm2 V Mb/s 1.5 V IOVCC 3.6 V 1.5 V IOVCC 3.6 V For in-band signals 115.2kb/s (SIR) 0.576 Mb/s in-band signals 1.15 Mb/s (MIR) For in-band signals. 7 7 Conditions Notes
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Electrical and Optical Specifications
Specifications hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values are at 25C and 3.0 V unless otherwise noted. Parameter Receiver RXD Output Voltage Logic High Logic Low Viewing Angle Peak Sensitivity Wavelength RXD Pulse Width (SIR) RXD Pulse Width (MIR) RXD Rise and Fall Times Receiver Latency Time Receiver Wake Up Time Transmitter Radiant Intensity (SIR) Radiant Intensity (MIR) Peak Wavelength Spectral Line Half Width Viewing Angle Optical Pulse Width (SIR) Optical Pulse Width (MIR, IOVCC 1.5 V) Optical Rise and Fall Times (SIR) Optical Rise and Fall Times (MIR) LED Current On (SIR) On (MIR) Current Off Transceiver TXD Input Current Supply Current High Low Shutdown Idle Active, Receive IH IL ICC1 ICC2 ICC3 10 -10 0.01 300 0.8 450 3.0 200 -200 nA nA A A mA VI VIH 0 VI VIL VCC=3.6 V, VSD VCC - 0.5, TA=25C VCC=3.6 V, VI(TXD) VIL,EI=0 VCC=3.6 V, VI(TXD) VIL 12,13 IEH IEH p 1/2 21/2 tpw tpw tr (EI) tf (EI) tr (EI) tf (EI) IVLED IVLED IVLED 30 1.41 148 1.6 217 50 30 60 150 0.005 4 9 15 30 875 35 60 2.23 260 600 40 72 180 1 28.8 72 mW/Sr TA=25C, 1/2 15, TXD VIH mW/Sr TA=25C, 1/2 15, TXD VIH nm nm s ns ns ns mA mA s tpw(TXD) = 1.6 s tpw(TXD) = 217 ns tpw(TXD) = 1.6 s tpw(TXD) = 1.6 s VVLED=VCC=3.6 V, VI(TXD) VIH VVLED=VCC=3.6 V, VI(TXD) VIH VVLED=VCC=3.6 V, VI(TXD) VIL VOH VOL 21/2 p tPW (SIR) tR, tF tL tRW 1 25 25 30 tPW(MIR) 200 IOVCC -0.2 0 30 880 7.5 750 100 50 100 IOVCC 0.4 V V nm s ns ns s s CL =10 pF CL =10 pF CL =10 pF 10 11 8,9 9 IOH=-200 A, EI 0.3 W/cm2 IOL=200 A 8 Symbol Min. Typ. Max. Units Conditions Notes
Notes: 7. An in-band optical signal is a pulse/sequence where the peak wavelength, p, is defined as 850 nm p 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification. 8. For in band signals 1.152 Mbps where 9 W/cm2 EI 500 mW/cm2. 9. For 0.576 Mbps in band signals 1.152 Mbps where 22.5 W/cm2 EI 500 mW/cm2 . 10. Latency is defined as the time from the last TXD light output pulse until the receiver has recovered full sensitivity. 11. Receiver wake up time is measured from the SD pin high to low transition or VCC power on, to valid RXD output. 12. Typical values are at EI = 10 mW/cm2. 13. Maximum value is at EI = 500 mW/cm2.
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tpw VOH 90% 50% 10%
VOL
tf
tr
Figure 4. RXD output waveform.
tpw LED ON 90% 50% 10% LED OFF
tr
tf
Figure 5. LED optical waveform.
TXD
LED
tpw (MAX.)
Figure 6. TXD `Stuck On' protection waveform.
SD
RX LIGHT
RXD
tRW
Figure 7. Receiver wakeup time waveform.
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Package Dimensions
MOUNTING CENTER
4.0 1.025
2.05
C L RECEIVER EMITTER
2.2 1.175 2.85 1.05 1.25 2.55
2.5
COPLANARITY: 0 to -0.2 mm
0.35 0.65 0.80
;;;; ;
4.0 8.0 3.0 1.85 C L 0.6 6.65 3.325
2.9
UNIT: mm TOLERANCE: 0.2 mm COPLANARITY: 0.1 mm MAX. PIN 1
Figure 8. Package outline dimensions.
8
Tape and Reel Dimensions
UNIT: mm
4.0 0.1 + 0.1 1.5 0 1.75 0.1 1.5 0.1
POLARITY PIN 8: LED A 8.4 0.1 PIN 1: CX 3.4 0.1 0.4 0.05 2.8 0.1 PROGRESSIVE DIRECTION 8.0 0.1 7.5 0.1 16.0 0.2
EMPTY (40 mm MIN.)
PARTS MOUNTED
LEADER (400 mm MIN.) EMPTY (40 mm MIN.)
OPTION # "B" "C" QUANTITY 001 021 UNIT: mm 178 330 60 80 500 2500
DETAIL A 2.0 0.5 13.0 0.5 B C
R 1.0 LABEL 21 0.8 DETAIL A 2 16.4 + 0 2.0 0.5
Figure 9. Tape and reel dimensions.
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Moisture-Proof Packaging
All HSDL-3210 options are shipped in moisture-proof packaging. Once opened, moisture absorption begins. This product is compliant to JEDEC level 4.
UNITS IN A SEALED MOISTURE-PROOF PACKAGE
PACKAGE IS OPENED (UNSEALED)
ENVIRONMENT LESS THAN 30C, AND LESS THAN 60% RH
YES
NO BAKING IS NECESSARY
YES
PACKAGE IS OPENED LESS THAN 72 HOURS
NO
PERFORM RECOMMENDED BAKING CONDITIONS
NO
Figure 10. Baking conditions chart.
Baking Conditions
If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. Packaging In Reels In Bulk Temp. 60C 100C 125C 150C Time 48 hours 4 hours 2 hours 1 hour
Recommended Storage Conditions
Storage Temp. Relative Humidity 10C to 30C Below 60% RH
Time from Unsealing to Soldering After removal from the bag, the parts should be soldered within three days if stored at the recommended storage conditions.
Baking should only be done once.
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Reflow Profile
MAX. 245C R3 R4
230
T - TEMPERATURE - (C)
200 183 170 150 125 100 R1
R2
90 sec. MAX. ABOVE 183C
R5
50 25 0 P1 HEAT UP 50 100 150 200 P3 SOLDER REFLOW 250 P4 COOL DOWN 300
t-TIME (SECONDS) P2 SOLDER PASTE DRY
Figure 11. Reflow graph.
Process Zone Heat Up Solder Paste Dry Solder Reflow Cool Down
Symbol P1, R1 P2, R2 P3, R3 P3, R4 P4, R5
T 25C to 125C 125C to 170C 170C to 230C (245C at 10 seconds max.) 230C to 170C 170C to 25C
Maximum T/time 4C/s 0.5C/s 4C/s -4C/s -3C/s
The reflow profile is a straight line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different T/time temperature change rates. The T/time rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-3210 castellation I/O pins are heated to a temperature of 125C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4C per second to allow for even heating of both the PC board and HSDL-3210 castellation I/O pins. 11
Process zone P2 should be of sufficient time duration (> 60 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 170C (338F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 230C (446F) for optimum results. The dwell time above the liquidus point of solder should be between 15 and 90 seconds. It usually takes about 15 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 90 seconds, the inter-
metallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 170C (338F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25C (77F) should not exceed -3C per second maximum. This limitation is necessary to allow the PC board and HSDL-3210 castellation I/O pins to change dimensions evenly, putting minimal stresses on the HSDL-3210 transceiver.
Appendix A : SMT Assembly Application Note
1.0 Solder Pad, Mask and Metal Solder Stencil Aperture
METAL STENCIL FOR SOLDER PASTE PRINTING
STENCIL APERTURE
LAND PATTERN
SOLDER MASK PCBA
Figure 12. Stencil and PCBA.
1.1 Recommended Land Pattern
C L 1.35 SHIELD SOLDER PAD
MOUNTING CENTER
1.25 0.10
2.05
0.775 1.75
FIDUCIAL 0.60 0.475 1.425 UNIT: mm 2.375 3.325
Figure 13. Land pattern.
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1.2 Recommended Metal Solder Stencil Aperture It is recommended that only a 0.152 mm (0.006 inches) or a 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern.
APERTURES AS PER LAND DIMENSIONS
t
w l
Figure 14. Solder stencil aperture.
Stencil Thickness, t (mm) 0.152 mm 0.127 mm
Aperture Size (mm) Length, l Width, w 2.60 0.05 0.55 0.05 3.00 0.05 0.55 0.05
1.3 Adjacent Land Keepout and Solder Mask Areas Adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. The minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. It is recommended that two fiducial crosses be placed at mid-length of the pads for unit alignment. Note: Wet/Liquid PhotoImageable solder resist/mask is recommended.
8.2
0.2
3.1
SOLDER MASK
3.0
UNITS: mm
Figure 15. Adjacent land keep-out and solder mask areas.
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Appendix B: PCB Layout Suggestion
The following PCB layout shows a recommended layout that should result in good electrical and EMI performance. Things to note: 1. The ground plane should be continuous under the part, but should not extend under the shield trace.
2. The shield trace is a wide, low inductance trace back to the system ground. 3. C1 is an optional VCC filter capacitor. It may be left out if the VCC is clean. 4. VLED can be connected to either unfiltered or unregulated power. If C1 is used, and if VLED is connected to VCC, the connection should be before the C1 cap.
A reference layout of a 2-layer Avago evaluation board for HSDL-3210 based on the guidelines stated above is shown below. For more details, please refer to Avago Application Note 1114, Infrared Transceiver PC Board Layout for Noise Immunity.
Top Layer
Bottom Layer
Figure 16. PCB layout suggestions.
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Appendix C: General Application Guide for the HSDL-3210 Infrared IrDA(R) Compliant 1.15 Mb/s Transceiver
Description The HSDL-3210, a low-cost and small form factor infrared transceiver, is designed to address the mobile computing market such as PDAs, as well as small embedded mobile products such as digital cameras and cellular phones. It is fully compliant to IrDA 1.3 low power specification from 9.6 kb/s to
1.152 Mb/s, and supports HP-SIR and TV Remote modes. The design of the HSDL-3210 also includes the following unique features: * Supports the serial interface for transceiver control (STC) specification. * Low passive component count. * Shutdown mode for low power consumption requirement. * Interface to input/output logic circuits as low as 1.5 V. * Adjustable optical power management
Interface to Recommended I/O chips The HSDL-3210's TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6 kb/s up to 1.152 Mbp/s is available at the RXD pin. The block diagram below shows how the IR port fits into a mobile phone and PDA platform.
SPEAKER
AUDIO INTERFACE DSP CORE MICROPHONE
ASIC CONTROLLER RF INTERFACE TRANSCEIVER MOD/ DE-MODULATOR MICROCONTROLLER USER INTERFACE IR
MOBILE PHONE PLATFORM
LCD PANEL
RAM IR
ROM
CPU FOR EMBEDDED APPLICATION
PCMCIA CONTROLLER
TOUCH PANEL
RS232C DRIVER
COM PORT
PDA PLATFORM
Figure 17. Mobile phone and PDA platform diagrams.
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Serial Interface Transceiver Control (STC) HSDL-3210 supports the serial interface for transceiver control specification that provides a common interface between the transceiver and controller. STC comprises a 3-wire interface: TXD/SWDAT, RXD/ARDAT and SCLK. This 3-wire interface abolishes the use of different modes and logic pins of existing transceivers. Instead registers on board the transceiver store
operating modes and states, thus electrical interface can be standardized across different vendors and transceivers. The diagram below shows the STC I/O between the transceiver and the IrDA controller. In normal operation, the TXD and RXD carry IR transmit and receive signals. In STC mode, SWDAT and SRDAT carry command and responses to and from the transceiver respectively.
Activity on the SCLK line determines whether the transceiver is to operate in the normal or STC mode. Please refer to Avago Application Note 1270 Serial Transceiver Control for Infrared Transceivers for further information on implementing STC using HSDL3210 as well as the lists of registers supported by HSDL3210.
TXD
INFRARED CONTROLLER (MASTER)
RXD
SCLK
TRANSCEIVER (SLAVE) STC - NORMAL MODE
SWDAT
(WRITE COMMAND)
SRDAT INFRARED CONTROLLER (MASTER)
(SEND RESPONSES)
SCLK
(CLOCK COMMAND / RESPONSE)
TRANSCEIVER (SLAVE) STC - COMMAND / RESPONSE MODE
Figure 18. STC block diagram.
16
STC Bus Protocol and Timing Diagrams Bus Protocol A set of commands is provided to handle the various transactions between the master and the slave. The general format is shown in Figure 19 whereby communications consist of a mandatory command phase followed by an optional response phase. The response phase occurs only when the slave needs to respond to a command. The command format consists of either 2 or 3 bytes command. The first byte, which is mandatory and common to all transactions, consists of the address/ index/control bits. There are two control fields. The first one is the "C" field which determines whether the command is a read or write operation or to act as a qualifier for a special operation. The second one is the "INDX" field whereby certain patterns define Special Transactions while others are for normal Data Transactions. The "ADDR" field is used to specify which transceiver the command is for. In a single transceiver system, this field is set to "000". The second byte contains the data payload for a 2 byte command. For a 3 byte command, this second byte is an 8 bit extended index. The third byte is the data payload when the extended index is used.
7 ADDR (3) INDX (4) C (1)
0 1st BYTE
7 DATA (SLAVE RESPONSE) or E_INDX (8)
0 2nd BYTE
7 DATA (SLAVE RESPONSE) (8)
0 3rd BYTE
Figure 19. General command format.
Write Transactions Write transactions are when the master writes data to the slave to select the slave's operational mode. This requires only the command phase as shown below.
ADDR [2:0]
INDX [3:0]
1
DATA
ADDR [2:0]
1
1
1
1
1
E_INDX[7:0]
DATA
Figure 20. Write command phase format.
Read Transactions Read transactions occur when the master queries the internal registers of the slave. The initial command phase is always followed by the response phase from the slave as shown below.
ADDR [2:0]
INDX [3:0]
0
ADDR [2:0]
1
1
1
1
0
E_INDX[7:0]
Figure 21a. Read command phase format.
DATA
Figure 21b. Slave response format.
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Bus Timing Diagrams The bus timings are designed to be simple and to minimize the effects of timing skew. This section discusses some key points with regard to bus timings and illustrates typical STC transactions with the use of waveforms. Bus Timing Notes 1. Data is transferred in Little Endian order, that is, the LSB on the first byte is transmitted first and the MSB of the second or third byte is transmitted last. 2. There are no gaps between bytes in the command or response phases. 3. Each byte in the command and response phase is preceded by a start bit on the SCLK line. 4. For data sampling and clocking, 4.1. Input data is sampled on the rising edge of SCLK. 4.2. Output data from the controller is clocked out on the falling edge of SCLK. 4.3. Output data from the slave is clocked out on the rising edge of SCLK.
5. The first low-to-high transition of SCLK indicates that an STC transition is pending. On receipt of his rising edge, the slave will disable the LED. The next SCLK low-to-high transition indicates the start cycle, followed by the command phase (which the controller puts out on the SWDAT line). The LED needs to be disabled since TXD and SWDAT are multiplexed. If the LED is not disabled, then the LED will pulse according to the SWDAT bit stream. 6. The LED is re-enabled (by the slave) on the last SCLK of the STC transaction bit stream. Normal infrared transmission can resume. No SCLK transitions should take place until the next STC transaction else the LED will be disabled. 7. The response from the slave is carried on the SRDAT line, which is multiplexed with RXD. The detector is (internally) disabled by the slave during the response phase. This is to prevent stray IR transitions from corrupting the SRDAT bit stream.
8. During a READ transaction, the controller holds the SWDAT line low for 1 clock after sending the ADDRESS and INDEX byte. It then holds it high and low for 3 clocks before the end of the transaction. This is to allow the transceiver to monitor the impending end of a transaction rather than by counting pulses. 9. When powered up, the transceiver is not ready to perform IR transmissions. The controller has to initialize the transceiver. The brief powered up sequences are: 9.1. On power up, an internally generated signal in the transceiver sets the 3 control registers: a) Control Register 0: * Bit 0: shutdown mode * Bit 1: RXD disabled * Bit 2: LED disabled b) Control Register 1: * Bit 0-7: SIR mode c) Control Register 2: * Bit 0-7: Power at 100% level 9.2. The controller has to initialize the transceiver by: a) Hold SWDAT low b) Toggle SCLK for at least 30 cycles The transceiver is in STC mode and ready to accept STC transactions.
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Bus Timing Sample Waveforms The following diagrams are sample waveforms for 2 byte write and read transactions and a 3 byte read transaction.
(A) SET CONTROL REGISTER 1 TO MIR MODE
1st BYTE
START C BIT INDEX ADDRESS START
2nd BYTE
DATA
SCLK
SWDAT
DON'T CARE
SRDAT
LED_DIS (INTERNAL)
Figure 22. Write waveform - set control register 1 to MIR mode.
(B) READ FROM CONTROL REGISTER 2 1st BYTE
START C BIT INDEX ADDRESS START
2nd BYTE DATA
SCLK
SWDAT
SRDAT
DON'T CARE
LED_DIS (INTERNAL)
STC_RXD_EN (INTERNAL)
Figure 23. Read waveform - read from control register 2 (transmitter power level).
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(C) READ DEVICE ID 1st BYTE
START C BIT
2nd BYTE DATA
START
3rd BYTE DATA
INDEX
ADDRESS START
SCLK
SWDAT
SRDAT
DON'T CARE
DON'T CARE
LED_DIS (INTERNAL)
STC_RXD_EN (INTERNAL)
Figure 24. Extended index read waveform - read device ID.
Electrical Specifications Timing specifications are given in the table and diagram below. Symbol tCKp tCKh tCKl tDOtv tDOth tDOrv tDOrh tDOrf tDIs tDIh Parameter SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Output Data Valid (from infrared controller) Output Data Hold (from infrared controller) Output Data Valid (from optical transceiver) Output Data Hold (from optical transceiver) Line float Delay Input Data Setup Input Data Hold Min. 250 60 80 0 40 40 60 10 5 Max. Units ns ns ns ns ns ns ns ns ns ns
40
tCKh SCLK
tCKl
tCKp
tDOtv
tDOth
IRTX/SWDAT
tDls IRRX/SRDAT
tDlh
tDOrv
tDOrh
tDOrf
Figure 25. Timing diagram. The link distance testing was done using typical HSDL-3210 units with National Semiconductor's PC87109 3V Super I/O controller and SMC's FDC37C669 and FDC37N769 Super I/O controllers. An IR link distance of up to 40 cm was demonstrated for SIR at full power. On the other hand, for MIR at full power, an IR link distance of up to 35 cm was demonstrated.
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Appendix D: Optical port dimensions for HSDL-3210
To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cone angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 30 and the maximum size corresponds to a cone angle of 60. In the figure below, X is the width of the window, Y is the height of the window, and Z is the distance
from the HSDL-3210 to the back of the window. The distance from the center of the LED lens to the center of the photodiode lens, K, is 5.1 mm. The equations for computing the window dimensions are as follows: X = K + 2*(Z + D)*tanA Y = 2*(Z + D)*tanA The above equations assume that the thickness of the window is negligible compared to the distance of the module from the back of the window (Z). If they
are comparable, Z' replaces Z in the above equation. Z' is defined as: Z' = Z + t/n where `t' is the thickness of the window and `n' is the refractive index of the window material. The depth of the LED image inside the HSDL-3210, D, is 3.17 mm. `A' is the required half angle for viewing. For IrDA compliance, the minimum is 15 and the maximum is 30. Assuming the thickness of the window to be negligible, the equations result in the following tables and graphs.
;;;;;;;; ;;;;;; ;;;;;;;;; ;;;;;; ;;;;;;;; ;;;;; ;; ;;
OPAQUE MATERIAL IR TRANSPARENT WINDOW Y X IR TRANSPARENT WINDOW K Z A D
OPAQUE MATERIAL
Figure 26. Window design diagram.
21
Module Depth (z) mm 0 1 2 3 4 5 6 7 8 9
Aperture Width (x, mm) Max. Min. 8.76 6.80 9.92 7.33 11.07 7.87 12.22 8.41 13.38 8.94 14.53 9.48 15.69 10.01 16.84 10.55 18.00 11.09 19.15 11.62
Aperture Height (y, mm) Max. Min. 3.66 1.70 4.82 2.33 5.97 2.77 7.12 3.31 8.28 3.84 9.43 4.38 10.59 4.91 11.74 5.45 12.90 5.99 14.05 6.52
APERTURE WIDTH (X) vs. MODULE DEPTH 25
APERTURE HEIGHT (Y) vs. MODULE DEPTH 16
20
APERTURE HEIGHT (Y) - mm
APERTURE WIDTH (X) - mm
14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 Y MAX. Y MIN. 7 8 9
15
10 X MAX. X MIN.
5 0
0
1
2
3
4
5
6
7
8
9
MODULE DEPTH (Z) - mm
MODULE DEPTH (Z) - mm
Figure 27. Aperture width (X) vs. module depth.
Figure 28. Aperture height (Y) vs. module depth.
Window Material Almost any plastic material will work as a window material. Polycarbonate is recommended. The surface finish of the plastic should be smooth, without any texture. An IR filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. Light loss should be measured at 875 nm. The recommended plastic materials for use as a cosmetic window are available from General Electric Plastics. Recommended Plastic Materials: Material Number Lexan 141L Lexan 920A Lexan 940A Light Transmission 88% 85% 85% Haze 1% 1% 1%
Shape of the Window From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. If the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. The amount of change in
the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm.
Refractive Index 1.586 1.586 1.586
Note: 920A and 940A are more flame retardant than 141L. Recommended Dye: Violet #21051 (IR transmissant above 625 nm).
Flat Window (First Choice)
Figure 29. Shape of windows.
Curved Front and Back (Second Choice)
Curved Front, Flat Back (Do Not Use)
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5988-8480EN 5989-4390EN May 28, 2006

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